In testing a semiconductor device by a semiconductor test system, the semiconductor test system provides test signals to the semiconductor device under test and compare the resulting output of the device under test with expected data to determine whether the semiconductor device works correctly or not. Since the modern semiconductor device, such as an LSI (large scale integrated circuit), has a large number of input-output pins, a semiconductor test system also has a large number of test channels corresponding to the pins of the semiconductor device to be tested.
In the semiconductor test industry, it is a common practice to test a plurality of semiconductor devices which have a relatively small number of pins by a semiconductor test system in parallel at the same time. One of the reasons is that a semiconductor test system has a large number of test channels to test a semiconductor device having a large number of pins, it is advantageous to divide the test channels to form a plurality of test stations to test a plurality of semiconductor devices at the same time to increase the test efficiency. In testing a plurality of IC devices at the same time by a plurality of test stations, the timings of the test signals among the test stations must be the same, i.e, the timing differences between the test stations must be adjusted to be zero.
FIG. 4 is a block diagram showing a structure of conventional semiconductor test system for testing a plurality of semiconductor devices in parallel at the same time by a plurality of test stations. For convenience of explanation, the example of FIG. 4 is to test two semiconductor devices and shows a test structure corresponding to only one pin P.sub.1a and P.sub.1b of the two respective semiconductor devices, DUT(a) and DUT(b) to be tested placed on the test stations ST1 and ST2. Thus, it should be noted that similar circuit arrangements are also provided for other pins of DUT(a) and OUT(b) in the actual test system.
The system of FIG. 4 includes a pattern generator 31, a timing generator 32, a wave formatter 33, variable delay circuits 34.sub.a and 34.sub.b, drivers 35.sub.a and 35.sub.b, analog comparators 36.sub.a and 36.sub.b, and logic comparators 38.sub.a and 38b. The pattern generator 31 generates a test signal and expected data. The test signal is provided to the timing generator 32 where the timing of the test signal is determined. The test signal is wave shaped by the wave formatter 33 such as in an RZ waveform or an NRZ waveform. The test signal from the wave formatter 33 is provided to the drivers 35.sub.a and 35.sub.b through the variable delay circuits 34.sub.a and 34.sub.b. Thus, the test signal is commonly applied to the pins P.sub.1a of DUT(a) and P.sub.1b of DUT(b).
The outputs of the DUT(a) and DUT(b) are compared with reference voltages (not shown) by the analog comparators 36.sub.a and 36.sub.b by the timings of strobe signals Sb. The outputs of the analog comparators 36.sub.a and 36.sub.b are provided to the logic comparators 38.sub.a and 38.sub.b whereby compared with the expected data from the pattern generator 31. In this arrangement, prior to the actual test of DUT(a) and DUT(b), the timing of the test signals at the pin P.sub.1a and P.sub.1b must be precisely adjusted.
To adjust the timings between the test stations ST1 and ST2, in the conventional semiconductor test system, delay times of the variable delay circuits 34.sub.a and 34.sub.b are adjusted by monitoring the timing at the inputs of DUT(a) and DUT(b). Typically, such adjustment of the timing phase is carried out station by station with the use of a test instrument such as an oscilloscope.
In this conventional technology, since the timing in each of the test stations is manually adjusted, the time required for such adjustment increases with an increase of the number of test stations and the number of pins of the devices to be tested. Further, since the variable delay time circuit in each of the station is to adjust the delay time common to all of the stations, the range of varying the delay time is large, which requires many circuit components to realize such range of delay times. Moreover, since the timing adjustment is carried out manually, such adjustment may involve errors such as reading errors caused by an operator.